The PCI-SIG (Peripheral Component Interconnect Special Interest Group), which includes about 900 companies, is responsible for discussing and shaping the PCIe bus standards.

This week, the association announced that it is making progress in developing a new version of PCIe 7.0 and has published version 0.5 for members. There is a possibility that the release specification of PCIe 7.0 could be approved as early as 2024. Currently, PCIe 7.0 development includes the following functional goals:

provides data transfer rates of 128 GB/s and up to 512 GB/s in both directions via PCIe x16 configuration;
use of PAM4 signal coding (amplitude modulation with 4 levels);
focus on signal parameters along the entire length of the channel;
achieve low latency and high reliability;
improving energy efficiency;
maintaining backward compatibility with previous generations of PCIe technology.

PCIe 7.0 technology aims to become a scalable switching solution for data-intensive markets such as 800G Ethernet, artificial intelligence, machine learning, hyper-scalable data centers, quantum and cloud computing. As PCIe technology continues to evolve to meet the high-bandwidth requirements of these applications, the PCIe 7.0 architecture will focus on signal quality while improving the power efficiency of signal processing.